Intelligent Data-centric Emerging Architecture Lab. Room 400525, Semiconductor Building Sungkyunkwan University (Suwon)
학력 Education
1995. 03 ~ 1999. 02 : Ph.D, Dept. of EE, KAIST (Efficient Motion Estimation Techniques and VLSI Architectures for Video Compression)
1992. 03 ~ 1994. 02 : MS, Dept. of EE, KAIST (On-chip Floating-point Unit Design for HK486 Microprocessor)
1988. 03 ~ 1992. 02 : BS, Dept. of EE, KAIST
약력/경력 Experience
2008. 03 ~ Present : Professor, Dept. of Semiconductor Systems Engineering, Sungkyunkwan University
2011. 03 ~ 2013. 04 : Program Director for System Semiconductor under Korea Evaluation Institute of Industrial Technology, Ministry of Knowledge Economy, Korea Government
2006. 09 ~ 2008. 02 : Assistant Professor, Dept. of Electronic Engineering, Korea Polytechnic University
1999. 03 ~ 2006. 08 : Senior Engineer, Telecom R&D Center in Samsung Electronics Co. Ltd
Low-power/Thermal Management Technology, 3D IC Technology
Network-on-chip, Memory Architecture and Interface, Optical Interface
논문 Journal Article
Min Su Kim, Yong Wook Kim, and Tae Hee Han, "System-Level Signal Analysis Methodology for Optical Network-on-Chip Using Linear Model-Based Characterization", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol 39, No. 10, Oct. 2020.
Yong Wook Kim, Jae Hoon Lee, and Tae Hee Han, "Extended Worst-case OSNR Searching Algorithm for Optical Network-on-Chip using a Semi-greedy Heuristic with Adaptive Scan Range", IEEE Access, Vol 8, pp. 125863-125873, July. 2020.
Sungchul Yoon, Sungho Jun, Yongkwon Cho, Kilwhan Lee, Hyukjae Jang, and Tae Hee Han, "Optimized Lossless Embedded Compression for Mobile Multimedia Applications", Electronics, Vol. 9, No. 5, May. 2020.
Jeong Beom Hong, Young Sik Lee, Yong Wook Kim, and Tae Hee Han, "Error-Vulnerable Pattern-Aware Binary-to-Ternary Data Mapping for Improving Storage Density of 3LC Phase Change Memory", Electronics, Vol. 9, No. 4, Apr. 2020.
Seung Chan Lee, and Tae Hee Han, "Q-Function-Based Traffic- and Thermal-Aware Adaptive Routing for 3D Network-on-Chip", Electronics, Vol. 9, No. 3, Feb. 2020.
Young Sik Lee, SoYoung Kim, and Tae Hee Han, "Aging-Resilient Topology Synthesis of Heterogeneous Manycore Network-On-Chip Using Genetic Algorithm with Flexible Number of Routers", Electronics, Vol. 8, No. 12, Dec. 2019.
Seongmin Ryu, Youngwoo Cho, and Tae Hee Han, "Timing Criticality-Aware Design Optimization Using BEOL Air Gap Technology on Consecutive Metal Layers", Electronics, Vol. 8, No. 11, Nov. 2019.
Tae Jin Kim, Tae Hee Han, "Developing a Portable Block Testbench and Reusable SOC Verification Scenarios Using IP-XACT Based Automation", Proceedings of 2020 Design & Verification Conference & Exhibition, USA, Mar. 2020