- 한재덕 | 회로 설계 및 자동화
-
- 한양대학교 융합전자공학부
- jdhan@hanyang.ac.kr
- 02-2220-2353
- https://niftylab.github.io/
- Bldg. 206 (Engineering Center - Main Building) #312-1, Hanyang University
- 학력 Education
-
- Ph.D. in Electrical Engineering and Computer Sciences, University of California, Berkeley, 2012 – 2017
- M.S. in Electrical Engineering and Computer Sciences, Seoul National University, 2007 – 2009
- B.S. in Electrical Engineering, Seoul National University, 2003 – 2007
- 약력/경력 Experience
-
- Assistant Professor, Hanyang University, 2019 – present
- SERDES Designer, Apple, 2017 – 2019
- Graduate Internships at Altera(now Intel FPGA), Intel, Xilinx, and Apple, 2012 – 2017
- 관심분야 Research Interest
-
- Design and Automatic Generation of Integrated Circuits
- 논문 Journal Article
-
- [JSSC’19] Stevo Bailey, Paul Rigge, Jaeduk Han, Richard Lin, Eric Chang, Howard Mao, Zhongkai Wang, Chick Markley, Adam Izraelevitz, Angie Wang, Nathan Narevsky, Woorham Bae, Steve Shauck, Sergio Montano, Justin Norsworthy, Munir Razzaque, Wen Hau Ma, Akalu Lentiro, Matthew Doerflein, Darin Heckendorn, Jim McGrath, Franco DeSeta, Ronen Shoham, Mike Stellfox, Mark Snowden, Joseph Cole, Dan Fuhrman, Brian Richards, Jonathan Bachrach, Elad Alon, and Borivoje Nikolic ́, “A Mixed-Signal RISC-V Signal Analysis SoC Generator with a 16nm FinFET Instance,” IEEE Journal of Solid-State Circuits, Special Issue on the 2018 IEEE Asian Solid-State Circuits Conference (ASSCC 2018), Jul. 2019.
- [JSSC’19] Angie Wang, Woorham Bae, Jaeduk Han, Stevo Bailey, Paul Rigge, Orhan Ocal, Zhongkai Wang, Kannan Ramchandran, Elad Alon, Borivoje Nikolić, “A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET,” IEEE Journal of Solid-State Circuits, Special Issue on the 2018 IEEE European Solid-State Circuits Conference (ESSCIRC 2018), vol.54, no.7, pp.1993-2008, Jun. 2019.
- [SSCL’18] Eric Chang, Nathan Narevsky, Jaeduk Han, Elad Alon, “An Automated SerDes Frontend Generator Verified with a 16nm Instance Achieving 15 Gb/s at 1.96 pJ/bit,” IEEE Solid-State Circuits Letters, Special Issue on the 2018 Symposium on VLSI Circuits (VLSIC 2018) , vol.1, no.12, pp.245-248, Dec. 2018.
- 연구실 이름 Laboratory Name
-
- The Nifty Chips LAB
- 연구분야 Field of Research
-
- 회로 설계 및 자동화
- High-speed operation circuit design
- Circuit design that exceeds the limit of operating speed of existing circuits - Highly integrated circuit and system design
- Circuit and system design capable of processing large amounts of data - Circuit design automation
- Increase productivity by automating the circuit design process