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IoT 시스템반도체 융합 인력 육성 센터

교수진

강진구 | VLSI설계 외
학력 Education
  • 1996 : Ph.D degree from North Carolina State University, NC
  • 1990 : M.S degree from New Jersey Institute of Technology, NJ
  • 1983 : B.S degree from Seoul National University
약력/경력 Experience
  • 1997 ~ : professor in school of electronics engineering at the Inha University, Incheon, South Korea.
  • 1996 ~ 1997 : senior design engineer in Intel (Portland, Oregon) involving I/O and timing circuit design(PLL) for Intel microprocessors
  • 1988 ~ 1996 : Texas Instrument Korea in the design center
관심분야 Research Interest
  • high-speed CMOS VLSI design
  • mixed mode IC design
  • high-speed serial interface design
논문 Journal Article
  • Yong-Hwan Moon, Kyung-Sub Son, Jin-Ku Kang, "A 2.41-pJ/bit 5.4-Gb/s Dual-Loop Reference-Less CDR With Fully Digital Quarter-Rate Linear Phase Detector for Embedded DisplayPort"
    IEEE Transactions on Circuits and Systems I: Regular Papers,Aug.2019
  • Kyung-Sub Son, Taek-Joon An, Yong-Hwan Moon, Jin-Ku Kang, "A 0.42 -3.45 Gb/s Referenceless Clock and Data Recovery Circuit with Counter-based Unrestricted Frequency Acquisition"
    IEEE Transactions on Circuits and Systems II: Express Briefs, 2019
  • Seong-Mun An, Kyung-Sub Son, Taek-Joon An, Jin-Ku Kang, "Design of a third-order delta-sigma TDC with error-feedback structure"
    IEICE Electronics Express, Vol.16, Issue 3, Feb. 10, 2019
연구실 이름 Laboratory Name
  • SICD LAB
연구분야 Field of Research
  • VLSI설계
  • mixed mode IC설계
  • 고속인터페이스
  • LED구동회로
  • FPGA 설계
  • 디지털시스템 설계
  • High-speed Serial Interface
    - PLL(Phase Locked Loop)
    - CDR (Clock and Data Recovery)
    - Tx, Rx Equalizer
    - SSCG (Speading-Spectrum Clock Generation)
    - PHY Design
  • Delay Management & Circuit
    - Two step, Delta-sigma TDC(Time-to-Digital Converter) Design
    - DLL (Delay Locked Loop) Circuit Design
    - All Digital PLL (Digital Clocking & RF Frequency Synthesis))
  • Digital VLSI Design, FPGA Prototyping
    - Serial Inteface Link Layer Design (DisplayPort, MIPI)
    - Image Processing (3D Enhancing) System FPGA Prototyping
    - 8B/10 B Encoder/Decoder, Byte Alignment
  • Artificial biological VLSI circuit
    - Power and Data Communication Circuit for Bio-implantable Device
    - Circuit Design for Bio-Application
  • Power Electronics control circuit
    - DC-DC converter for LED Driver
    - LED Color Control Circuit