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Creative Innovation
IoT 시스템반도체 융합 인력 육성 센터

교수진

권기원 | 신소자 TEG 개발
학력 Education
  • 9/1995 – 1/2001 STANFORD UNIVERTY, Stanford, CA
    Ph.D. degree in Materials Science and Engineering (Advisor: Robert Sinclair)
    Thesis title: Reactions and microstructural behavior at the Cu/Ta interfaces.
  • 34/1998 – 1/2000 STANFORD UNIVERSITY, Stanford, CA.
    Master of Science degree in Electrical Engineering (Advisor: S. Simon Wong)
    - Analog/mixed circuit design,
    - Device physics and silicon technology.
  • 53/88 – 2/1990 KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY, Seoul, Korea
    Master of Science degree in Materials Science and Engineering (Advisor: Jai-Young Lee)
    – Hydrogen storage metals and their applications to the heat pump.
  • 73/1984 – 2/1988 SEOUL NATIONAL UNIVERSITY, Seoul, Korea
    Bachelor of Science degree in Metallurgical Engineering
    - Physical metallurgy and solid state physics.
약력/경력 Experience
  • 3/2007 – present Sungkyunkwan University, Suwon, Korea
    Professor, College of Information and Communication Engineering
    – High Speed Serial Interface: USB, HDMI, LVDS, Inductive Link
    – Energy Harvesting System, PMIC/BMIC
    – Design for Testability (DFT) of 3-D IC.
    – Standards and Specification.
    – Cross-Point Memory Architecture with Resistive Memory Cells
    – Non-Volatile Memory IP.
  • 13/2006 – 2/2007 Hanyang University, Ansan, KOREA.
    Assistant Professor, Division of Materials and Chemical Engineering
    – Electronic Materials and Devices Lab.
  • 11/2001 – 3/2006 SAMSUNG ELECTRONICS CO., LTD, Hwaseong, KOREA.
    Principal Design Engineer in Advanced Technology Development Team (2/2005 – 2/2006)
    – In charge of low power technology (Transistor, circuit & logic level approaches)
  • Principal Design Engineer in DRAM Design Team (1/2001 – 2/2005)
    – Super High Performance DRAM design (tRC of 10ns, 10Gbps Data Rate)
    – Advanced DRAM design including Direct Rambus DRAM and XDR DRAM.
    – New memory development (PRAM, Scalable Gain-Cell Memory, Multimedia DRAM)
    – Core circuit design for DRAM.
  • 16/2000 – 1/2001 MAXIM INTEGRATED PRODUCTS, Sunnyvale, CA
    Associate Member of Technical Staff
    – 16-bit D/A converter design.
    – Digital potentiometer design
  • 16/1999 – 9/1999 INTEL Corporation, Portland, OR, Summer Intern
    – Diffusion and drift of copper in intermetallic dielectrics.
    – Life time test (Bias Temperature Stressing) of intermetallic dielectrics.
    – Copper/tantalum interaction at high temperature.
  • 12/1990 – 7/1995 SAMSUNG ELECTRONICS CO., Semiconductor R&D Center, Kiheung, Korea
    Staff Engineer
    – In charge of developing thin capacitor dielectric films (SiO2, SiN, Ta2O5 and [BaSr]TiO3)
    – Process modules to fabricate three dimensional capacitor structures for DRAM applications.
    – Maintenance of chemical vapor deposition systems, furnaces, and sputters.
  • Leading member
    – Joint development project with LAM RESEARCH CO., Fremont, CA (5/1991 – 11/1992)
    – Development of CVD system for Ta2O5 thin film.
  • Acting member
    – Joint 256Mb DRAM development project with NEC, Tokyo, Japan (1/1994 – 6/1995).
    – Members: D. Chin, C.-G. Hwang, M.-Y. Lee, S.-T. Ahn, S.-W. Kim, E.S. Kim, & myself
관심분야 Research Interest
  • Integrated Process and TEG Platform Technology Development for Emerging Semiconductor DevicesMinistry of Science, ICT and Future Planning, 2019~2022(신소자 TEG 개발, Neural Network H/W platform 설계, 등)
  • 1Reconfigurable Logic Device and Architecture Development
    Ministry of Science, ICT and Future Planning, 2016~2021
    (나노스위치 집적공정개발, 재구성 아키텍처 개발, 기계학습 H/W 설계, 등)
  • 1Emerging Non-Volatile Memories and their Applications
    Samsung Electronics, 2015~2020
    (TCAM/STT-MRAM/ReRAM core, peri circuit 설계, 등)
  • 1Technology Trends in Vertical NAND Flash Memory
    Samsung Electronics, 2016~2016
    (Vertical NAND Flash 벤치마킹, QLC 연구 등)
  • 1Development of Evaluation Technology in 3D IC
    Ministry of Trade, ICT and Industry and Energy, 2016~2020
  • 1Standards in Healthcare Sensor
    Ministry of Trade, ICT and Industry and Energy, 2016~2019
논문 Journal Article
  • Jong-Moon Choi, et. al., “A Highly Linear Neuromorphic Synaptic Device based on Regulated Charge Trap/Detrap,”IEEE, Electron Devices Letters, September 2019 (Early Access)
  • 2Sung-Yong Kim, et. al.,“Dynamic Power Reduction of TCAM using Selective Precharging of Match lines”, IEEK J. Semiconductor Technology and Science, (submitted)
  • 3Jisu Min, et. al., “A Study of Read Margin Enhancement for 3T2R Nonvolatile TCAM Using Adaptive Bias Training” IEEE, Transactions on VLSI Systems, vol. 27, no. 8, pp. 1840-1850, August 2019
  • 4Xuefan Jin, Kee-Won Kwon, Young-Shig Choi, and Jung-Hoon Chun, “A Dual-loop Phase Locked Loop with Frequency to Voltage Converter”, IEEK J. Semiconductor Technology and Science, vol. 19, no. 3, pp. 292-299, June 2019
  • 5Eun-Je Park, Jong-Moon Choi, and Kee-Won Kwon, “Behavior Modeling for Charge Storage in Single-poly Floating Gate Device” J. of Nanoscience and Nanotechnology, vol.19, no.10, pp.6727-6731, October 2019
연구실이름 laboratory name
  • CUSTOM IC DESIGN LAB