Creative Innovation
IoT 시스템반도체 융합 인력 육성 센터

교수진

이한호 | 집적회로 및 시스템 설계 외
학력 Education
  • 2000.03 : Ph.D. Electrical & Computer Engineering, University of Minnesota, Minneapolis, Minnesota , USA .
  • 1996.06 : M.S. Electrical & Computer Engineering, University of Minnesota, Minneapolis, Minnesota , USA .
  • 1993.02 : B.S. Electronics Engineering, Chungbuk National University, Korea .
약력/경력 Experience
  • 2010.08 ~ 2011.08 : Visiting Scholar, Bell Labs., Alcatel-Lucent, Murray Hill, New Jersey, USA.
  • 2005.03~2006.02 : Visiting Researcher, Electronics & Telecommunications Research Institute (ETRI), Deajeon, Korea.
  • 2002.08 ~ 2004.08 : Assistant Professor, Dept. of Electrical and Computer Engineering, University of Connecticut, Storrs, USA.
관심분야 Research Interest
  • Cryptographic algorithm and architectures for Internet of Things (IoT)
  • Hardware cryptographic architecture design (Post-quantum cryptography, Homomorphic Encryption, Lattice Cryptography)
  • High-Performance Forward Error Correction (FEC) Architectures
  • Artificial Intelligent (AI) HW design (인공지능 하드웨어 설계)
  • DSP and FEC Architectures for Communications
논문 Journal Article
  • Thang Xuan Pham, Tuy Nguyen Tan, Hanho Lee, "Minimal-Set Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes,"
    IEEE Transactions on Circuits and Systems II, Jul 29. 2020. (IF 2.814, SCIE)
  • Phap Duong-Ngoc, Tuy Nguyen Tan, and Hanho Lee, "Efficient NewHope Cryptography Based Facial Security System on a GPU,"
    IEEE Access, vol. 8, no. 1, pp. 108158-108168, June 2020. (IF 4.098, Q1)
  • Tuy Nguyen Tan, Tram Thi Bao Nguyen and Hanho Lee, "High Efficiency Ring-LWE Cryptoprocessor Using Shared Arithmetic Components,"
    Electronics, 9(7), 1075, June 2020.
연구실 이름 Laboratory Name
  • DIS LAB
연구분야 Field of Research
  • 집적회로 및 시스템 설계
  • 시스템온칩(SoC) 설계
  • 하드웨어 보안
  • Digital VLSI and System-on-a-Chip (SoC) Design for Communications
  • Cryptography Algorithm and Architecture for IoT
  • Forward Error Correction (FEC) Architectures for 400Gb/s Optical Communications (e.g: LDPC, BCH, RS codes)
  • LDPC Decoder Architecture for 60GHz mmWave WPAN systems
  • Polar Decoder Architecture
  • High-speed Low-complexity FFT/IFFT processor for MIMO-OFDM communications